Graduate students: Vaibhav Karkare

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Graduate Student Researcher Electrical Engineering Department University of California, Los Angeles Vaibhav Karkare received the B.E. degree in Electrical and Electronics Engineering and the M.Sc. degree in Physics from the Birla Institute of Technology & Science (B.I.T.S.), Pilani in 2006 and the M.S. degree in Electrical Engineering from University of California, Los Angeles (UCLA) in 2009. He is currently a Ph.D. candidate at UCLA, EE. Vaibhav is interested in the design of bio-potential recording and processing circuits. Specifically, he is interested in the development of scalable, reconfigurable, digitally-assisted solutions for biosignal acquisition. He is also interested in the development of algorithms and DSP architectures for biomedical data compression.

Contents 1 Research Highlights 2 Teaching Experience 3 Industry Experience 4 Publications 5 Awards and Honors 6 Contact Information

Research Highlights

Graduate Student Researcher, EE, UCLA, USA

• A 200 mV-saturation-tolerant, 23-bit DR, 1 uVrms I/P referred rms noise, 1 uW @1.2 V/0.4V, reconfigurable EMG/EEG/ECG/LFP/AP recording front-end using VCO-based ADCs in 65-nm bulk CMOS. (in progress)

• A 1 sq. inch, 6 g., discrete prototype wireless recording system (provides 8 hour battery life), currently being used for experiments to analyze traumatic brain injuries.

• Union of supports reconstruction technique for compressively sampled neural action potentials. Provides an overall 21-times data-rate reduction

• The first unsupervised, online, multi-channel clustering chip that provides 240x data-rate reduction while consuming 75 uW in a 65-nm CMOS process

• A 64-channel spike-sorting chip in 90-nm CMOS that consumes 130 uW, 7-times lower than state-of-the-art designs

Visitng Scholar, Imec, Leuven, Belgium

• Analysis of linearity requirements for a neural recording ADC

• Analysis and modeling of non-idealities for a passive charge sharing SAR-CR ADC

Summer Student Resarcher, Inter-University Center for Astronomy and Astrophysics, Pune, India

• Studied techniques for measurement of optical aberrations using defocussed images

• Implemented the numerical solutions for estimating aberrations in 'C' (using numerical recipes in C)

Teaching Experience

• Course development TA for EE216B: VLSI Signal Processing, Winter 2012, UCLA
• TA for EE 115C - Digital Integrated Circuits, Winter 2009, UCLA
• TA for MS Online Graduate course: EEM 216A - VLSI Circuits and Systems, Fall 2008, UCLA
• Co-instructor for MS (Part-time) course: Digtial Integrated Circuits, 2007, BITS - Pilani, (Distance Learning Division)

Industry Experience

Intern, Mixed-Signal Design, Ethernet PHY Team, Broadcom Corp., Irvine, USA

• Design modifications to a 90-deg phase-shift DLL for reduced supply voltage
• Design of a SAR CR-ADC -- comparator and input buffer, circuit and layout design

Engineer, Digital Design, Memory BIST Team Qualcomm India Pvt. Ltd., Bangalore, India

• Design, Integration, and Verification of Memory BIST for QCT ASICs
• Development of test plan and verification methodology for memory BIST

Intern, Digital Design, Memory BIST Team, Qualcomm India Pvt. Ltd., Bangalore, India

• Design and Implementation of VHDL-based, verification methodology for connectivity analysis of memory BIST

Publications

• V. Karkare, S. Gibson, and D. Marković, "A 75μW, 16-Channel Neural Spike-Sorting Processor with Unsupervised Clustering," IEEE J. Solid-State Circuits, to appear

• V. Karkare and D. Marković, "Ultra-low-power Links for Brain Probing," in Proc. 2012 IEEE Subthreshold Microelectronics Conference, Oct 2012. (Invited)

• V. Karkare, S. Gibson, C.-H. Yang, H. Chen, D. Marković, "A 75μW, 16-Channel Neural Spike-Sorting Processor with Unsupervised Clustering," in Proc. Int. Symposium on VLSI Circuits (VLSI'11), June 2011, pp. 252-253.

• Z. Charbiwala, V. Karkare, S. Gibson, D. Markovic, and M. Srivastava, "Compressive Sampling of Neural Action Potentials Using a Learned Union of Supports," Body Sensors Networks Conference, May 2011.

• V. Karkare, S. Gibson, and D. Marković, "A 130-uW, 64-Channel Neural Spike-Sorting DSP Chip," IEEE J. Solid-State Circuits, vol. 46, no. 5, pp. 1214-1222, May 2011.

• H. Fariborzi, M. Spencer, V. Karkare et al., "Analysis and Demonstration of MEM-Relay Power Gating," in Proc. IEEE Custom Inegrated Circuits Conference (CICC'10), Sep. 2010, pp. 1-4.

• C.-H. Yang, S. Gibson, V. Karkare, and D. Markovic, "Hardware Architecture of O-Sort Spike Clustering," in AMA-IEEE Medical Technology Conf. Individualized Healthcare, Mar. 2010.

• V. Karkare, "A 130 uW, 64-Channel, Spike-Sorting DSP Chip," M.S. Thesis, UCLA, December 2009.

• V. Karkare, S. Gibson, and D. Markovic, "A 130 uW, 64-Channel Spike-Sorting DSP Chip," in IEEE Asian Solid-State Circuits Conference (ASSCC'09), Nov. 2009, pp. 289-292.

• R. Chandler, S. Gibson, V. Karkare, S. Farshchi, D. Markovic, and J. W. Judy, "A System-Level View of Optimizing High-Channel-Count Wireless Biosignal Telemetry," in Proc. Int. IEEE Engineering in Medicine and Biology Conf. (EMBC'09), Sept. 2009, pp. 5525-2230.

• S. Gibson, R. Chandler, V. Karkare, D. Markovic, and J. W. Judy, "An Efficiency Comparison of Analog and Digital Spike Detection," in Proc. 4th Int. IEEE EMBS Conf. on Neural Eng. (NER'09), May 2009, pp. 423-428.

• V. Karkare, S. Gibson and D. Markovic, "A 64-Channel Implantable Spike-sorting DSP Chip" presented at the IEEE International Solid-State Circuits Conference Student Forum (ISSCC'09), Feb 2009.

Awards and Honors

• Edward K. Rice Outstanding MS Student Award, Henry Samueli School of Engineering and Applied Sciences, UCLA, 2009.

• Outstanding Master of Science Award, Department of Electrical Engineering, UCLA, 2009.

• QUALStar Award, Qualcomm, India for contribution to development of verification methodologies for memory BIST, 2007.

• Best Graduating Student Award, Department of Physics, B.I.T.S. Pilani, 2006.

Contact Information

Email: vkarkare@ucla.edu