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Neural Spike Sorting - DejanWiki

Neural Spike Sorting

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Background

Figure 1: Neural signals are composed of activity from multiple neurons surrounding the electrode.

Electrophysiology, the technique of recording electrical signals from the brain using microelectrodes, is a common method used in neuroscience, biology, and psychology experiments. The electrical activity captured from individual neurons, termed “single-unit activity”, has proven to be extremely useful for obtaining a better understanding of how the brain processes information. Moreover, in recent years decoding single-unit activity has shown to be a promising technique for controlling brain-machine interfaces (BMIs) such as neural prostheses. However, the neural signals recorded by these microelectrodes are frequently composed of activity from multiple neurons surrounding the electrode (Fig. 1). Therefore, in order to decode the information contained in the neural signals so that they can be used for scientific study or as input to BMIs, spike sorting, the process of attributing each spike to the originating neuron, is necessary. Currently spike sorting is normally performed in software. There are a number of problems with this approach.

Spike sorting requires quite complex signal processing. In typical science experiments, the raw data is saved for subsequent offline spike sorting using software on a personal computer. Many spike-sorting algorithms require human supervision, and since spike sorting one channel of data usually takes at least the real-time length of the experiment or longer (depending on the algorithms used), this process can be extremely time-consuming for the experimenter. Even if automatic algorithms are used, personal computers can process only one channel of data at a time, so the processing time increases linearly with the number of recording channels used. Moreover, the experimenter is unable to utilize the data until the experiment is over, thereby rendering real-time applications infeasible.

Furthermore, recent advances in data-acquisition technology allow for the recording of hundreds of channels simultaneously, but a higher number of channels leads to a higher data rate. For instance, 100 channels sampled at 25 kSa/s using 12-bit resolution would lead to 30 Mbps of data. Wireless transmission at this data rate cannot be achieved at power levels required from implantable electronics; the FCC-approved Medical Implant Communication System (MICS) is limited to 25 μW of transmit power and 300 kHz of bandwidth [1], which limits data rates to much less than 30 Mbps. Therefore, data must be transferred from the animal to a computer via thick cables. These cables restrict the natural movement of the animal, which limits the quality and types of experiments that can be performed. And in many clinical applications such as BMIs, wireless recording is a necessity.

We therefore plan to develop a digital signal processor (DSP) architecture for performing real-time spike sorting on multichannel extracellular recordings. Performing unsupervised, real-time spike sorting in hardware, simultaneously on many channels, would not only save on processing time, but might also provide researchers with whole new experimental paradigms. Wireless, on-site spike sorting would aid in providing experimenters with instantaneous information about the neurons, such as their tuning functions as a stimulus is varied. These signals could also be used to “close the loop” by delivering signals back to the brain, enabling a whole new class of neurophysiological and neuropsychological experiments. Performing spike sorting in hardware would also achieve enough data reduction to enable the wireless transmission of data, thereby eliminating the need for cables. This would open the door for new types of experiments in which the activity of the brain is investigated as animals move freely, possibly even in their natural environments. It may also allow for recording from species that have never before been recorded, such as freely flying bats. This hardware could also serve as a prototype for the DSP in a full implantable, wireless recording system (Fig. 2) for clinical applications like neural prostheses, in which spike sorting must be performed on-chip and in real time before the signals can be decoded into commands for the prosthesis, and epilepsy treatment, in which real-time information about the neurons must be available in order to detect and prevent seizures.

Figure 2: Wireless Recording System

Spike Sorting

The neural signal processing chain for single-unit activity is shown in Fig. 3. The first steps are spike detection, the process of separating spikes from background noise, and alignment, the process of aligning all detected spikes to a common point. Once the spikes have been identified, spike sorting can take place. Spike sorting is possible because each neuron produces a different, distinct shape (as seen by the electrode) that is assumed to remain constant throughout a recording session. As a result, the first step in spike sorting is feature extraction, in which spikes are transformed into a certain set of features, such as principal components, that emphasize the difference between spikes from different neurons. After feature extraction, some form of dimensionality reduction (not pictured) typically takes place, in which feature coefficients that best separate spikes are identified and stored for subsequent clustering and the rest are discarded. Finally, spikes are classified into different groups, corresponding to different neurons, based on the extracted feature coefficients; this process is referred to as clustering. The result, the signal of interest to the experimenter and to BMIs, is the spike times for each neuron.

The first step in this project is to decide which spike-detection and spike-sorting algorithms to implement. Quite a large number of algorithms have been published in the literature, and many independent groups have evaluated individual algorithms using different, often biological, data sets. In our preliminary work [2], we developed synthetic data sets in order to obtain an accurate, unbiased comparison between algorithms. We compared a number of different spike-detection and feature-extraction algorithms over a wide range of SNRs in order to determine which are optimal for hardware implementation. Alignment, dimensionality reduction, and clustering algorithms will be evaluated in the near future.

Figure 3: Signal Processing Chain

Design Goals

Hardware for spike sorting must be low-power in order to prevent heat-related tissue damage and low-area in order to be implantable. The most widely referenced power limit is 0.8 mW/mm2 [3], which is dictated by chronic tissue overheating. Some believe that the power limit is actually lower, around 0.2 mW/mm2 [4]. The lower limit was observed in recordings over a long period (several months), but it has not been confirmed that temperature was the root cause of the problem. The actual power limit for implantable electronics is influenced by the packaging technology. However, the packaging area should also be minimized in order to be implantable, which requires area minimization of the DSP. Therefore, the power limit of 0.8 mW/mm2 will be assumed as a constraint for neural-DSP hardware, but lower targets will actually be achieved.

The low-power and low-area requirements lead to requirements on the algorithms implemented in the hardware; specifically, these algorithms must be as computationally simple as possible while maintaining an acceptable level of performance. Furthermore, because this DSP will be used in real-time applications, additional requirements for the algorithms used are that they be automatic, unsupervised, and real-time.

The work by our collaborators involves recordings from 128 channels, so the proposed DSP will be designed to process 128 channels simultaneously. The proposed DSP architecture is scalable to future systems that operate with upwards of 1000 channels.

We assume that the input to the DSP is amplified, filtered (100 Hz - 10 kHz), digital neural waveforms. The chip will be programmable to output combinations of the following:

  • raw data
  • extracted spike waveforms
  • spike time stamps
  • spike IDs

Existing designs either provide only spike detection for multi-channel processing [5], or they provide detection and feature extraction only for a single channel [6-7]. We will use a modular architecture that will allow the chip to be configured for simultaneous processing on 2n (n≤N) channels. Inactive cores will be power-gated to reduce leakage power when the chip operates for less than 2N channels. Techniques like supply voltage scaling, power gating, and interleaving may also be used.

The spike sorting algorithms will be chosen with careful consideration of the target technology. Only complexity/accuracy-optimal algorithms will be used. Some initial work has been done with this. (Or maybe we will make algorithm choice customizable, in which case someone could choose to use a non-optimal algorithm?)

References

  1. FCC Rules and Regulations, “MICS Band Plan”, Part 95, Jan. 2003.
  2. S. Gibson, J.W. Judy, and D. Markovic, "Comparison of Spike-Sorting Algorithms for Future Hardware Implementation," in Proc. Int. IEEE Engineering in Medicine and Biology Conf. (EMBC'08), Aug. 2008, pp. 5015-5020.
  3. T.M. Sees, H. Harasake, G.M. Saidel, and C.R. Davies, “Characterization of tissue morphology, angiogenesis, and temperature in adaptive response of muscle tissue to chronic heating,” Lab.Investigation, vol. 78(12), 1998, pp. 1553-1562.
  4. Reid Harrison, Associate Professor, Department of Electrical and Computer Engineering, University of Utah. IC-Neurotech Workshop, Los Angeles, CA. Personal correspondence. May 28, 2008.
  5. M. Rizk et al., "A single-chip signal processing and telemetry engine for an implantable 96-channel neural data acquisition system," J. Neural Engineering, vol. 4, pp. 309-332, 2007.
  6. R. Olsson, and K. Wise, "A Three-Dimensional Neural Recording Microsystem with Implantable Data Compression Circuitry," ISSCC'05, pp. 558–559.
  7. M. Chae et al., "A 128-Channel 6mW Wireless Neural Recording IC with On-the-Fly Spike Sorting and UWB transmitter," ISSCC'08, pp. 146-147.

Acknowledgments

  1. National Science Foundation (NSF) funding support
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