Chip Gallery

2011 Chips

	Direct-sampling Rx (65nm CMOS) Functionality: fractional decimation from arbitrary RF carriers up to 2.7GHz to any LTE baseband frequency. Performance: 14mW, noise figure < 3dB
	Publications: A-SSCC 2011	Designer: Rashmi Nanda

	Online neural-spike clustering (65nm CMOS) Functionality: real-time unsupervised clustering simultaneously for 16 channels. Performance: 75uW, chip area: 1.3 x 1.9 mm, data-rate reduction: 240x
	Publications: VLSI 2011	Designer: Vaibhav Karkare

	Cognitive radio spectrum sensing (65nm CMOS) Functionality: Wideband (200 MHz) spectrum sensing processor with adaptive threshold and sensing time. Performance: 7.4mW, chip area: 1.3 x 1.9 mm, Pd > 0.9, Pfa < 0.1, 200 kHz spectral resolution, sensing time < 50 ms for SNR > - 5dB and adjacent-channel INR < 30 dB.
	Publications: VLSI 2011 JSSC 2012	Designers: Tsung-Han Yu Chia-Hsiang Yang

	FPGA with hierarchical interconnect (65nm CMOS) Functionality: Reconfigurable hardware, 2K LUTs. Performance: 1.1 GOPS/mW peak efficiency, 0.27 V < Vdd < 1V, fmax = 400 Mhz.
	Publications: VLSI 2011	Designers: Cheng C. Wang Fang-Li Yuan

2010 Chips

	8x8 LTE MIMO (65nm CMOS) Functionality: 8x8 MIMO sphere decoder with hard/soft decision and LTE-compliant FFT front end. The chip implements mix-radix reconfigurable FFT that supports 128, 256, 512, 1024, 1536, and 2048 points. The FFT design methodology is archived in the journal paper referenced below. Performance: 13.8mW (LTE mode: 5.8mW, LTE FFT: 2.8mW)
	Publications: VLSI 2010 JSSC 2012	Designers: Chia-Hsiang Yang Tsung-Han Yu

	NEMS VLSI blocks (1um lithography) Jack Raper Award for Outstanding Technology Directions Functionality: Microelectromechanical relay circuits (flip-flop, SRAM, DRAM, adder, ADC, 7:3 compressor). Performance: functional circuits, 12V operation
	Publications: ISSCC 2010 JSSC 2011	Designers: Fred Chen (MIT) Matther Spencer (UC Berkeley) Cheng C. Wang

2009 Chips

	64-Channel Neural Spike-Sorting Chip (90nm CMOS) Functionality: Neural-spike detection, alignment, and feature extraction for 64 channels. Performance: 130uW (2uW/ch), data-rate reduction: 11x
	Publications: A-SSCC 2009 JSSC 2011	Designer: Vaibhav Karkare

	16x16 MIMO Sphere Decoder (90nm CMOS) ISSCC/DAC Student Design Contest Winner Functionality: Multi-core (16 cores) 16x16 MIMO sphere decoder with hard outputs. Performance: 2.9-275mW
	Publications: ESSCIRC 2009	Designer: Chia-Hsiang Yang

2006 Chip

	4x4 SVD (90nm CMOS) 2007 David J. Sakrison Memorial Prize Functionality: Adaptive 4x4 blind-tracking SVD for 16 channels. Performance: 2 GOPS/mW, 20 GOPS/mm2
	Publications: VLSI 2006 JSSC 2007	Designer: Dejan Marković