EE216B VLSI Signal Processing
This course concentrates on DSP architecture design and optimization within high-level description that can be mapped to hardware. Topics include study of circuit and architecture techniques in energy-area-performance space, automated wordlength reduction, scheduling and retiming, and application of these concepts to various algorithms in emerging communication, multimedia and healthcare applications. The course is useful for algorithm designers who consider hardware constraints and for circuit designers who prototype DSP algorithms in hardware.
Students learn how to map DSP algorithms into a description optimized for hardware constraints. Two key outcomes are:
- Hardware-friendly algorithm development
- Optimized hardware implementation that minimizes energy and area
This is accomplished through a systematic methodology for algorithm modeling, architecture exploration, and hardware optimizations. Multi-disciplinary nature of the material that includes DSP theory, VLSI circuits and architectures provides much-needed interaction between the disciplines that are traditionally kept separate.
- Tue & Thu, 4:00-5:50pm
- BH 8500 (campus map)
- Dejan Markovic (56-147E Eng-IV, by appointment)
- Office hours: Tue & Thu 6-7pm (BH 8500) | MSOL: Thu 11am-12pm PST (ZOOM)
- Homeworks (4): 20%
- Project: 30%
- Midterm: 25%
- Final: 25%