EE115C Digital Electronic Circuits
This course focuses on introductory-level digital IC design. The topics include:
- Transistor operation in deep-submicron,
- In-depth discussion of the current equations and parasitic capacitances of CMOS transistors
- Study of CMOS inverter and logic gates, including
- gate delay calculations,
- power consumption,
- transistor sizing,
- placement for speed/power improvement using both analytical as well as simulation (spice) based studies.
- Dynamic logic gates,
- Sequential circuits,
- Adder architectures.
Course grades are available through EEweb course interface.
Spring 2013 Schedule
- Mon & Wed, 8:00-9:50am, 5249 Boelter Hall (map: interactive)
- Dis. 1A: Tue 12:00-12:50pm, 5233 Mathematical Sciences
- Dis. 1B: Thu 12:00-12:50pm, 5264 Boelter Hall
- Dis. 1C: Fri 2:00-2:50pm, 6704 Geology
- Office hours
- Sina: Mon 12:00-1:00pm, Wed 4:00-6:00pm, 53-145 ENG IV
- TA. Abishek: Wed & Fri, 12:00-1:00pm, 67-112 ENG IV (TA Room)
About EE115C Classwiki
This page is designed primarily for use by UCLA students enrolled in EE115C. Local resources are restricted to the registered students, who also have edit privileges. This allows everyone in class to collectively share notes about good design practices, tips & tricks for using CAD tools, interesting articles related to course material, etc. Active users will be rewarded with course participation credit. Mediawiki keeps track of edits and this feature will be used to help calculate the reward points. The same mechanism can be used to detect malicious users -- they may be disabled access to local resources and left without CAD support. Outside visitors may freely browse "public access" links. Full access may be granted upon request.
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